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ICs for Consumer Electronics
Field Mixer SDA 9270
Data Sheet 01.96
SDA 9270 Revision History: Previous Version: Page 24 25 25 25 27
Current Version: 01.96
Subjects (changes since last revision) HYTHL1 control bits have been increased to 6 HYTHL2 control bits have been increased to 6 HYTHH1 control bits have been increased to 6 HYTHH2 control bits have been increased to 6 Clock inputs CLL, SCA, SCAD: SCA clock frequence MIN changed to 12 MHz SCAD clock specification added Fall/rise time specification added I2C-Bus specification extended to fast mode Max. average supply current: 200 mA
27 29
Edition 01.96 This edition was realized using the software system FrameMaker(R). Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1996. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
General Information
Table of Contents 1 1.1 1.2 1.3 1.4 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.8.1 2.8.2 2.8.3 2.8.4 3 3.1 3.2 3.3 4 5 6
Page 4 4 5 6 7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Input Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Field Interpolation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Motion Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Field Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SYNC-Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C-Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C-Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics (Assuming Recommended Operating Conditions) . . . . . . . 25 25 26 28
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Semiconductor Group
3
Field Mixer
SDA 9270
Preliminary Data 1 Introduction
CMOS
The Field Mixer SDA 9270 is an add-on component for the Siemens MEGAVISION IC set which enables the system to reduce large area and line flickering of interlaced TV standards. 1.1 * * * * * Features P-MQFP-80-1
High performance line flicker reduction algorithm Two input data formats (4:1:1 and 4:2:2) I2C-Bus control P-MQFP-80 package 5 V supply voltage
Supported MEGAVISION features * Multipicture (still in picture, picture in still, 9xpicture) * Still field * Zoom New MEGAVISION features * Still frame * Background still field MEGAVISION features not supported * 4:4:4 * Colored frame insertion (FRM) Type SDA 9270 Ordering Code Q67100-H5158 Package P-MQFP-80-1
Semiconductor Group
4
01.96
SDA 9270
1.2
Block Diagram
Semiconductor Group
5
SDA 9270
1.3
Pin Configuration
Semiconductor Group
6
SDA 9270
1.4 Pin No.
Pin Description Name Type S S Description Supply voltage (VSS) for digital parts and input stages Supply voltage (VDD) for digital parts and input stages Data input UV of channel A (see Data Format) Data input Y of channel A (see Data Format) Data input UV of channel B (see Data Format) Data input Y of channel B (see Data Format)
10, 30, 47, 54, 70 VSS 11, 31, 48, 55, 71 VDD 74 .. 80,1 2 .. 9 12 .. 19 20 .. 27 28 29 32 33 34 35 36 37 38 39 40 41 42 43.. 46,49..52 53,56 .. 62 63 64 65 66 67
UVA0 .. 7 I/TTL YA0 .. 7 YB0 .. 7 RENB OEBB SACQ SARQ SCAD SCA REN SACIN SARIN VS2 BLN BLN2 CLL YQ0 .. 7 I/TTL I/TTL UVB0 .. 7 I/TTL
Q/TTL RAM enable field memory B Q/TTL Output enable port B of field memory B Q/TTL Serial column address output Q/TTL Serial row address output I/TTL I/TTL I/TTL I/TTL I/TTL I/TTL I/TTL I/TTL I/TTL Serial address clock input Clock signal for data input RAM enable / input from SDA 9220 Serial column address / input from SDA 9220 Serial row address / input from SDA 9220 100 Hz vertical synchronization signal Blanking signal, high level indicates active video line Blanking signal / double line frequency System clock
Q/TTL Data output Y of channel Q (see Data Format)
UVQ0 ..7 Q/TTL Data output UV of channel Q (see Data Format) ZM VS1 TEST SCL SDA I/TTL I/TTL I/TTL I IQ Zoom control input (HIGH level for zoom mode) 50 Hz vertical synchronization signal Test pin; must be connected to VSS for normal operation I2C-Bus clock line I2C-Bus data line
Semiconductor Group
7
SDA 9270
Pin Description (cont'd) Pin No. 68 69 72 73 S: supply, Name BLN3 VS3 RENA OEBA I: input, Type Description
Q/TTL Blanking signal / BLN2 delayed Q/TTL Vertical synchronization signal (switched raster) Q/TTL RAM enable field memory A Q/TTL Output enable port B of field memory A Q: output, TTL: digital (TTL)
2
System Description
The device generates at its output an opportune sequence of 100/120 Hz fields derived by processing the field A and the field B which are stored in 2 external field memories and made available to the SDA 9270 on 2 separate input ports of 16 bit width each. The device SDA 9270 generates also control signals for the SDA 9251 which are necessary to operate the TV - SAMs in the Frame mode, that is to write the incoming information alternatively in one or the other field memory. Additionally the device generates a vertical sync pulse which has to be synchronized with the respective field output. A horizontal blanking signal in phase with the output data is also made available.
Semiconductor Group
8
SDA 9270
2.1
Input Data Format
The SDA 9270 accepts for the input channels A and B two different input formats (I2C-Bus : INFOR) with two possible sample frequency relations of Y : (B-Y) : (R-Y). The representation of the samples is programmable separately for luminance and chrominance signals as positive dual code or 2's complement code (I2C-Bus : INCODL, INCODC) Data Pin Yx7 Yx6 Yx5 Yx4 Yx3 Yx2 Yx1 Yx0 UVx7 UVx6 UVx5 UVx4 UVx3 UVx2 UVx1 UVx0 Xab: X: signal component Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 V07 V06 Data Format 4:1:1 INFOR = 0 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02 Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00 4:2:2 Parallel INFOR = 1 Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 U05 U04 U03 U02 U01 U00 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 V07 V06 V05 V04 V03 V02 V01 V00 a: sample number b: bit number Yx,UVx : x : A,B
The amplitude resolution for each input signal component is 8 bit, the maximum clock frequency is 30 MHz. Consequently the SDA 9270 is dedicated for applications in high quality digital video systems. The data input stages and the internal data multiplexer operate with a special input clock (SCA). For applications in the Siemens MEGAVISION System the SCA-clock is identical with the memory output clock.
Semiconductor Group
9
SDA 9270
2.2
Output Data Format
The data format for the output channel Q will be a 4:2:2 parallel format in 2's complement code representation.
Data Pin YQ7 YQ6 YQ5 YQ4 YQ3 YQ2 YQ1 YQ0 UVQ7 UVQ6 UVQ5 UVQ4 UVQ3 UVQ2 UVQ1 UVQ0 Xab: X: signal component
4:2:2 Parallel Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 U05 U04 U03 U02 U01 U00 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 V07 V06 V05 V04 V03 V02 V01 V00 a: sample number b: bit number
Semiconductor Group
10
SDA 9270
2.3
Field Interpolation and Switching
In order to reduce the annoying line and edge flickering a frame rate upconversion is implemented. The upconversion includes a combination of interpolation algorithms which are determined via I2C-Bus and then selected automatically depending on the picture motion content. The field interpolation and switching block accepts at its input the data of the two channels A and B, which are the combined luminance and chrominance information respectively of the field A and the field B. The field rate is 100/120 Hz. A fallback mode which corresponds to the operating mode AABB of the original MEGAVISION system is made available. This mode is selected automatically in case of non-standard input signals carrying unstable sync informations or it can be forced via I2C-Bus. 2.4 Motion Detection
The motion detection output is switched in a 25/30 Hz frame synchronous raster. As input signals for this block are accepted the luminance signal components of the input channels A and B. By comparing the two fields the motion detector generates an information about 3 possible motion content levels: LOW, MEDIUM and HIGH. 2.5 Field Memory Control
The Field Mixer SDA 9270 has to provide the two external field memories - composed of TV-SAM SDA 9251 - with two pairs of control signals. One pair RENA and RENB enables the MEGAVSION system to write the incoming field A and field B information alternately into one field memory block and then into the other. A second pair of control signals OEBA and OEBB enables alternately the output back channels of field memory A and B for the noise reduction in the Picture Processor SDA 9290. Because of the timing the serial address signals SAC and SAR generated by the MSC SDA 9220 must be delayed by 4 SCAD-clock periods. This delay is implemented in the SDA 9270. The Sync signals VS1 and BLN and the clock signal SCAD are used as timing reference signals. 2.6 Frame Synchronization
In order to synchronize the data flows within field memories and Field Mixer and to coordinate the signal information with the associated deflection control the Field Mixer SDA 9270 has to generate 25 Hz picture frame sync signals. One 25 Hz frame sync signal is necessary for generating the field memory control signals RENA, RENB, OEBA, OEBB with a pattern repetition of 25 Hz each. This signal is synchronized to the front end side video signal of the MEGAVISION block and uses therefore as input signals the 50 Hz vertical sync signal VS1 generated by the MSC SDA 9220 and the horizontal blanking signal BLN.
Semiconductor Group 11
SDA 9270
A second 25 Hz frame sync signal is needed in the interpolation and switching block and in the VS3 pulse generation block for assuring an output data sequence of the channel Q synchronized with the VS3 pulse. As reference signals for this second frame sync signal are used the 100 Hz vertical sync signal VS2 and the blanking signal BLN2 both generated by the MSC SDA 9220. 2.7 SYNC-Signal Generation
This functional block generates a couple of sync signal needed in the processing stages following the Field Mixer device. This couple includes the vertical sync signal VS3 and the horizontal blanking signal BLN3. All these signals are synchronized with the output channel Q. 2.8 2.8.1 I2C-Bus I2C-Bus Address 0001111 2.8.2 write: S00011110A S: A: P: NA: Start condition Acknowledge Stop condition Not Acknowledge Subaddress A Data Byte A ***** A P I2C-Bus Format
An automatical address increment function is implemented.
Semiconductor Group
12
SDA 9270
After switching on the IC (RES=0), all bits are set to defined states. Particularly:
Register 00 01 02 03 04 05 06 07 08 09 0A
Default Value 00H 00H 00H 00H 40H F4H 58H 20H F8H 70H E8H
Register 0B 0C 0D 0E 0F 10 11 12 13 14 15
Default Value 50H 03H 0DH 08H 28H A5H 55H 0AH 18H 05H 03H
Semiconductor Group
13
SDA 9270
2.8.3
Subadd. (Hex.) D7
I2C-Bus Commands
Data Byte
D6
D5
D4
D3
D2
D1
D0
00
LINFRA
PIXLIN
WRMODE2
WRMODE1
WRMODE0
NRDEL
RASTER1
RASTER0
01
0
INCODL
INCODC
INFOR
FALLBACK
FIWIN2
FIWIN1
FIWIN0
02
ZMMODE1
ZMMODE0
0
0
INTMODLL1
INTMODLL0 INTMODCL1
INTMODCL0
03
RDMODE1
RDMODE0
0
0
INTMODLM1 INTMODLM0 INTMODCM1
INTMODCM0
04
EDCONST1
EDCONST0
0
0
INTMODLH1 INTMODLH0 INTMODCH1
INTMODCH0
05
CFHENA07
CFHENA06
CFHENA05
CFHENA04
CFHENA03
CFHENA02
CFHENA01
CFHENA00
06
CFHENA17
CFHENA16
CFHENA15
CFHENA14
CFHENA13
CFHENA12
CFHENA11
CFHENA10
07
CFHENB07
CFHENB06
CFHENB05
CFHENB04
CFHENB03
CFHENB02
CFHENB01
CFHENB00
08
CFSCHA007 CFSCHA006 CFSCHA005 CFSCHA004 CFSCHA003 CFSCHA002 CFSCHA001
CFSCHA000
09
CFSCHA107 CFSCHA106 CFSCHA105 CFSCHA104 CFSCHA103 CFSCHA102 CFSCHA101
CFSCHA100
0A
CFSCHA017 CFSCHA016 CFSCHA015 CFSCHA014 CFSCHA013 CFSCHA012 CFSCHA011
CFSCHA010
0B
CFSCHA117 CFSCHA116 CFSCHA115 CFSCHA114 CFSCHA113 CFSCHA112 CFSCHA111
CFSCHA110
0C
CFSCHB007 CFSCHB006 CFSCHB005 CFSCHB004 CFSCHB003 CFSCHB002 CFSCHB001
CFSCHB000
0D
CFSCHB107 CFSCHB106 CFSCHB105 CFSCHB104 CFSCHB103 CFSCHB102 CFSCHB101
CFSCHB100
0E
CFSCHB017 CFSCHB016 CFSCHB015 CFSCHB014 CFSCHB013 CFSCHB012 CFSCHB011
CFSCHB010
Semiconductor Group
14
SDA 9270
I2C-Bus Commands (cont'd)
Subadd. (Hex.) D7 D6 D5 D4 Data Byte
D3
D2
D1
D0
0F
CFSCHB117
CFSCHB116
CFSCHB115
CFSCHB114
CFSCHB113
CFSCHB112
CFSCHB111
CFSCHB110
10
MDTHL21
MDTHL20
MDTHL11
MDTHL10
0
MDBLTH2
MDBLTH1
MDBLTH0
11
MDTHU21
MDTHU20
MDTHU11
MDTHU10
MDTHM21
MDTHM20
MDTHM11
MDTHM10
12
0
0
HYTHL15
HYTHL14
HYTHL13
HYTHL12
HYTHL11
HYTHL10
13
0
0
HYTHL25
HYTHL24
HYTHL23
HYTHL22
HYTHL21
HYTHL20
14
0
0
HYTHH15
HYTHH14
HYTHH13
HYTHH12
HYTHH11
HYTHH10
15
0
0
HYTHH25
HYTHH24
HYTHH23
HYTHH22
HYTHH21
HYTHH20
Semiconductor Group
15
SDA 9270
2.8.4
Detailed Description Subaddress 00
Bit D7
Name LINFRA
D6
PIXLIN
D5...D3
WRMODE*
D2
NRDEL
D1...D0
RASTER*
Function Lines per frame: 0: 625 lines per frame (default value) 1: 525 lines per frame Pixels per line: 0: 864 pixels per line (default value) 1: 858 pixels per line Write Mode: 000 : Normal operation: field memory A and field memory B are written alternately (default value) 001 : Still picture A and B: writing is suppressed for both field memories 010 : Still picture A: writing is suppressed for field memory A, all incoming fields are written to field memory B 011 : Still picture A: writing is suppressed for field memory A, every second field is written to field memory B (Field Mode B) 100 : Still picture B: writing is suppressed for field memory B, all incoming fields are written to field memory A 101 : Still picture B: writing is suppressed for field memory B, every second field is written to field memory A (Field Mode A) 110 : Reserved 111 : Reserved Noise Reduction Delay: conditions: 2 field memory configuration, WRMODE = 000 0: Data delay for recursive filtering is one frame (default value) 1: Data delay for recursive filtering is one field Deflection Raster control: 00: Control by interpolation algorithm (default value) 01: 10: 11:
Note: SDA 9220 programming: - Subaddress 00 / D7 (EXSYN): For EXSYN=1 WRMODE=100 is required. - Subaddress 01 / D7 (FLDM), Subaddress 02 / D7 (STB): FLDM and STB should always be set to 0. - Subaddress 00 / D1, D0 (VDM): VDM must be set to 00.
Semiconductor Group 16
SDA 9270
Subaddress 01 Bit D6 Name INCODL Function Coding of luminance input data: 0: positive dual code (default value) 1: 2's complement Coding of chrominance input data: 0: positive dual code (default value) 1: 2's complement Input data format: 0: 4:1:1 luminance, chrominance parallel (8+4 wires) (default value) 1: 4:2:2 luminance, chrominance parallel (8+8 wires) Fallback mode: 0: Normal operation (default value) 1: programmed fall back mode is activated for current display Field identification window Definition of a time window. Switching from fall back mode to programmed display mode is not performed until the field identification algorithm is working in a stable condition during the programmed time. 000 : 7 field periods (default value) 001 : 15 field periods : : 110 : 55 field periods 111 : 63 field periods
D5
INCODC
D4
INFOR
D3
FALLBACK
D2...D0
FIWIN
Semiconductor Group
17
SDA 9270
Subaddress 02 Bit D7..D6 Name ZMMODE Function zoom mode (enabled only if pin ZM = 1 and RDMODE = 00) 00: field sequence at output Q: AABB (default value) 01: field sequence at output Q: ABAB 10: display with raster correction 11: Reserved luminance interpolation mode, low degree of motion 00: field sequence AABB without interpolation () (default value) 01: field sequence ABAB without interpolation () 10: Schroder algorithm () 11: Hentschel algorithm () chrominance interpolation mode, low degree of motion 00: field sequence AABB without interpolation () (default value) 01: field sequence AABB without interpolation () 10: field sequence ABAB without interpolation () 11: linear interpolation ()
D3..D2
INTMODLL
D1..D0
INTMODCL
Semiconductor Group
18
SDA 9270
Subaddress 03 Bit D7..D6 Name RDMODE Function read mode 00: both inputs are used (interpolation enabled if ZM = 0) (default value) 01: only input A is used (without interpolation) 10: only input B is used (without interpolation) 11: Reserved luminance interpolation mode, medium degree of motion 00: field sequence AABB without interpolation () (default value) 01: field sequence ABAB without interpolation () 10: Schroder algorithm () 11: Hentschel algorithm () chrominance interpolation mode, medium degree of motion 00: field sequence AABB without interpolation () (default value) 01: field sequence AABB without interpolation () 10: field sequence ABAB without interpolation () 11: linear interpolation ()
D3..D2
INTMODLM
D1..D0
INTMODCM
Semiconductor Group
19
SDA 9270
Subaddress 04 Bit D7..D6 Name EDCONST Function edge detector gain factor 00: 2 01: 3 (default value) 10: 4 11: 5 luminance interpolation mode, high degree of motion 00: field sequence AABB without interpolation () (default value) 01: field sequence ABAB without interpolation () 10: Schroder algorithm () 11: Hentschel algorithm () chrominance interpolation mode, high low degree of motion 00: field sequence AABB without interpolation () (default value) 01: field sequence AABB without interpolation () 10: field sequence ABAB without interpolation () 11: linear interpolation ()
D3..D2
INTMODLH
D1..D0
INTMODCH
Subaddress 05 Bit D7..D0 Name CFHENA0 Function Hentschel algorithm, 8-bit coefficient a0 (2's complement) (default value F4H)
Subaddress 06 Bit D7..D0 Name CFHENA1 Function Hentschel algorithm, 8-bit coefficient a1 (2's complement) (default value 58H)
Semiconductor Group
20
SDA 9270
Subaddress 07 Bit D7..D0 Name CFHENB0 Function Hentschel algorithm, 8-bit coefficient b0 (2's complement) (default value 20H)
Subaddress 08 Bit D7..D0 Name CFSCHA00 Function Schroder algorithm, 8-bit coefficient a00 (2's complement) (default value F8H)
Subaddress 09 Bit D7..D0 Name CFSCHA10 Function Schroder algorithm, 8-bit coefficient a10 (2's complement) (default value 70H)
Subaddress 0A Bit D7..D0 Name CFSCHA01 Function Schroder algorithm, 8-bit coefficient a01 (2's complement) (default value E8H) Subaddress 0B Bit D7..D0 Name CFSCHA11 Function Schroder algorithm, 8-bit coefficient a11 (2's complement) (default value 50H)
Subaddress 0C Bit D7..D0 Name CFSCHB00 Function Schroder algorithm, 8-bit coefficient b00 (2's complement) (default value 03H)
Semiconductor Group
21
SDA 9270
Subaddress 0D Bit D7..D0 Name CFSCHB10 Function Schroder algorithm, 8-bit coefficient b10 (2's complement) (default value 0DH)
Subaddress 0E Bit D7..D0 Name CFSCHB01 Function Schroder algorithm, 8-bit coefficient b01 (2's complement) (default value 08H)
Subaddress 0F Bit D7..D0 Name CFSCHB11 Function Schroder algorithm, 8-bit coefficient b11 (2's complement) (default value 28H)
Subaddress 10 Bit D7..D6 Name MDTHL2 Function threshold for low degree of motion (small blocks) 00: 0 01: 64 10: 128 (default value) 11: 192 threshold for low degree of motion (large blocks) 00: 0 01: 64 10: 128 (default value) 11: 192 threshold in front of the blocking module 000: 4 001: 8 : : 111: 32 (default value 101)
D5..D4
MDTHL1
D2..D0
MDBLTH
Semiconductor Group
22
SDA 9270
Subaddress 11 Bit D7..D6 Name MDTHU2 Function threshold for high degree of motion (small blocks) 00: 384 01: 512 (default value) 10: 640 11: 768 threshold for high degree of motion (large blocks) 00: 384 01: 512 (default value) 10: 640 11: 768 threshold for second field difference (small blocks) 00: 64 01: 128 (default value) 10: 192 11: 256 threshold for second field difference (large blocks) 00: 64 01: 128 (default value) 10: 192 11: 256
D5..D4
MDTHU1
D3..D2
MDTHM2
D1..D0
MDTHM1
Subaddress 12 Bit D5..D0 Name HYTHL1 Function hysteresis threshold, low degree of motion (large blocks) 000000: 1 000001: 1 000010: 2 : 111111: 63 (default value 001010)
Semiconductor Group
23
SDA 9270
Subaddress 13 Bit D5..D0 Name HYTHL2 Function hysteresis threshold, low degree of motion (small blocks) 000000: 1 000001: 1 000010: 2 : 111111: 63 (default value 011000)
Subaddress 14 Bit D5..D0 Name HYTHH1 Function hysteresis threshold, high degree of motion (large blocks) 000000: 1 000001: 1 000010: 2 : 111111: 63 (default value 000101)
Subaddress 15 Bit D5..D0 Name HYTHH2 Function hysteresis threshold, high degree of motion (small blocks) 000000: 1 000001: 1 000010: 2 : 111111: 63 (default value 000011)
Semiconductor Group
24
SDA 9270
3 3.1
Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values min. max. 70 125 125 260 10 C C C C s 0 - 65 Unit Remark
Parameter Operating temperature Storage temperature Junction temperature Soldering temperature Soldering time Input voltage Output voltage Supply voltages Supply voltage Differentials
TA Tstg Tj TS tS VI VQ VS
V
- 0.3 V VDD + 0.3 V V - 0.3 V VDD + 0.3 V V - 0.3 - 0.25 6 0.25 V V
VCC respectively VCC respectively
between any internally nonconnected supply pins of the same kind, see Pin Description MIL STD 883C method 3015.6, 100 pF, 1500 all inputs/outputs
Total power dissipation ESD protection
Ptot
ESD -2
1 2
W kV
Latch-up protection
- 100
100
mA
All voltages listed are referenced to ground (0 V, VSS) except where noted. Note: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
Semiconductor Group
25
SDA 9270
3.2
Recommended Operating Conditions Symbol Limit Values min. typ. 5 25 max. 5.5 70 V C 4.5 0 Unit Test Conditions
Parameter Supply voltages Ambient temperature All TTL Inputs High-level input voltage Low-level input voltage All TTL outputs High-level output voltage Low-level output voltage
VDD VCC TA
VIH VIL VQH VQL
2.0 V 0 2.4
VDD
0.8
1 V V
0.4
V
IQH = - 2.0 mA IQL = 3.0 mA
Clock TTL Inputs CLL, SCA, SCAD Clock frequency Low time High time Rise time Fall time SCA - CLL skew time 12 27 30 MHz ns ns 5 5 0 15 ns ns ns Diagram on page 22 Rise/fall time 5 ns
tWL tWH tTLH tTHL tSK
10 10
I2C Bus (all values are referred to min(VIH) and max(VIL)) High-level input voltage Low-level input voltage SCL clock frequency Inactive time before start of transmission Set-up time start condition Hold time start condition SCL low time SCL high time Set-up time DATA
VIH VIL fSCL tBUF tSU;STA tHD;STA tLOW tHIGH tSU;DAT
3V 0 0 1.3 0.6 0.6 1.3 0.6 100
VDD
1.5 400
1 V kHz s s s s ns
Semiconductor Group
26
SDA 9270
3.2
Recommended Operating Conditions (cont'd) Symbol Limit Values min. typ. max. s 300 300 0.6 3 ns ns s mA 0 Unit Test Conditions
Parameter Hold time DATA SDA/SCL rise times SDA/SCL fall times Set-up time stop condition Low-level output current
tHD;DAT tR tF tSU;STO IOL
fSCL = 400 kHz
Note: Under this conditions the functions given in the circuit description are fulfilled. Nominal conditions specify mean values expected over the production spread and are the proposed values for interface and application. If not stated otherwise, nominal values will apply at TA = 25 C and the nominal supply voltage.
Semiconductor Group
27
SDA 9270
3.3
Characteristics (Assuming Recommended Operating Conditions) Symbol Limit Values min. max. 200 mA All VCC and VDD pins Unit Remark
Parameter Average supply current
IS
All Digital Inputs (including I/O inputs) Input capacitance Input leakage current
CI II
- 10
10 10
pF A
Not tested; max. 7 pF for SCA, CLL
TTL Inputs: YA, YB, UVA, UVB (referenced to SCA) Set-up time Input hold time
tSU tIH
7 6
ns ns
TTL Inputs: REN, SACIN, SARIN (referenced to SCAD) Set-up time Input hold time
tSU tIH
7 6
ns ns
TTL Inputs: BLN, BLN2, VS1, VS2, ZM (referenced to CLL) Note: For BLN a jitter of 1 CLL is allowed Set-up time Input hold time
tSU tIH
7 6
ns ns
TTL Outputs: YQ, UVQ (referenced to CLL) Hold time Delay time
tQH tQD
6 25
ns ns
CL = 30 pF
TTL Outputs: VS3, BLN3 (referenced to CLL) Hold time Delay time
tQH tQD
6 25
ns ns
CL = 30 pF
TTL Outputs: RENA, RENB, SACQ, SARQ (referenced to SCAD) Hold time Delay time
tQH tQD
6 20
ns ns
CL = 50 pF
Semiconductor Group
28
SDA 9270
3.3
Characteristics (Assuming Recommended Operating Conditions) (cont'd) Symbol Limit Values min. max. Unit Remark
Parameter
TTL Outputs: OEBA, OEBB (referenced to SCAD) Hold time Delay time
tQH tQD
6 20
ns ns
CL = 30 pF
Input/Output: SDA (referenced to SCL; Open Drain Output) Low-level output voltage
VOL
0.5
V
at IOL = max
Note: The listed characteristics are ensured over the operating range of the integrated circuit.
Semiconductor Group
29
SDA 9270
4
Application Information
Semiconductor Group
30
SDA 9270
5
Waveforms
Timing Diagram Data Input/Output Referenced to the Clock
Timing Diagram Clock Skew SCA - CLL
Semiconductor Group 31
SDA 9270
6
Package Outlines
P-MQFP-80-1 (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 32
Dimensions in mm
GPM05249
SDA 9270
Semiconductor Group
33

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